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A 2.5nJ/b 0.65V 3-to-5GHz Subbanded UWB Receiver in 90nm CMOS
May 2006 tapeout
The die micrograph to the left is of a non-coherent 0-to-16Mb/s UWB receiver using 3-to-5GHz subbanded PPM signaling is implemented in a 90nm CMOS process. The RF and mixed-signal baseband circuits operate at 0.65V. Using duty-cycling, adjustable BPFs, and an energy-aware baseband, the receiver achieves 2.5nJ/b and 10^(-3) BER with -99dBm sensitivity at 100kb/s. |
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A 3.1-10.6GHz 100Mb/s Pulse-based UWB Radio Receiver Chipset
Collaboration with Raul Blazquez, Brian Ginsburg, Johnna Powell, Michael Scharfstein, and David Wentzloff August 2006 A complete 3.1-10.6GHz UWB receiver using 500MHz-wide sub-banded binary phase shift keyed (BPSK) pulses has been specified, designed and integrated as a three chip and planar antenna solution from a team of 6 graduate students working over 3 years. The system includes a custom designed 3.1-10.6GHz planar antenna, direct-conversion RF front-end, 500MS/s analog to digital converters, and a parallelized digital back-end for signal detection and demodulation. A 100Mb/s wireless link has been established with this chipset. A BER of 10^(-3) was recorded at -80dBm at a rate of 100Mb/s for properly acquired packets in the lowest frequency band. Bit-scaling of the ADC from 1 to 5 bits reveals a 4dB improvement in the link budget. The video on the left shows wirelessly transmitted images, and real-time downconverted and received wireless pulses. In particular, I was responsible for system integration, debugging, and testing. |
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A BiCMOS UWB 3.1-10.6 GHz Front-end
June 2004 tapout
This chip is a direct-conversion receiver for FCC-compliant UWB Gaussian-shaped pulses that are transmitted in one of fourteen 500MHz-wide channels within the 3.1-10.6GHz band. The receiver is fabricated in 0.18µm SiGe BiCMOS. The packaged chip consists of an unmatched wideband low-noise amplifier (LNA), filter, phase-splitter, 5GHz ISM band switchable notch filter, and baseband channel-select filters/buffers. The required quadrature single-ended LO signals are generated externally. The average conversion gain and input P1dB are 32dB and 41dBm, respectively. The unmatched LNA provides a system noise figure of 3.3-5dB over the entire band. The chip draws 30mA from 1.8V. To verify the unmatched LNA's performance in a complete system, wireless testing of the front-end embedded in a full receiver at 100Mbps reveals a 10^(-3) BER at -80dBm sensitivity. The notch filter suppresses out-of-band interferers and reduces the effects of intermodulation products that appear in the baseband. BER improvements of an order of magnitude and greater are demonstrated with the filter. |
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50Mb/s UWB Prototype Transciever
Collaboration with Nathan Ackerman, Raul Blazquez, Kyle Gilpin, Brian Ginsburg, and Vivienne Sze August 2005 This prototype transceiver is built using discrete components. It communicates in a 500MHz band centered at 5.355GHz using BPSK pulses with a pulse repetition frequency of 50MHz. The received signal is down-converted to I/Q baseband signals using off-the-shelf discrete components. The baseband signals are digitized by dual 8-bit Atmel ADCs. Synchronization and demodulation are implemented in a Xilinx Virtex II FPGA enabling real-time communication at 50Mb/s. The transceiver communicates with a PC over USB2.0. Real-time one-way transmission of a video stream over the air has been demonstrated at a 50Mb/s raw data rate using this transceiver. In particular, I was responsible for the RF front-end receiver and analog baseband. |
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A Baseband UWB Transceiver
Collaboration with Raul Blazquez and Puneet Newaskar June 2003 tapeout This is the lab's first UWB-related chip, consisting of an LNA, FLASH time-interleaved ADC, pulse transmitter, self-biased PLL, and digital baseband. The chip is integrated in a 0.18µm process. 193kbps of wireless transmission is demonstrated. In particular, I was responsible for the PLL, LNA, pulse transmitter, and final integration. |
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µAMPS-1 Wireless Sensor Node
Collaboration with Nathan Ickes and Piyada Phanaphat June 2002 The µAMPS-1 microsensor node uses commercial, off-the-shelf (COTS) components for rapid construction. A µAMPS-1 node consists of a stack of three or four printed circuit boards. The top board contains the Bluetooth radio, including the RF TRX circuitry and the FPGA used for digital coding and decoding. The second board contains an Intel StrongARM processor and associated RAM and flash ROM. Also on the processor board are an acoustic sensor (microphone, amplifier, filter, and analog-to-digital converter) and a collection of dc/dc power converters that service the entire node. The optional third board in the stack is an additional sensor module to replace the acoustic sensor on the processor board. The µAMPS-1 node can be easily adapted to different applications by designing an appropriate sensor board. In particular, I was responsible for the RF board. |
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MIT's 6.270 Autonomous LEGO Robot Competition
Collaboration with Brian Lin January 2001 "Don't Worry," the blue robot shown to the left, is an autonomous LEGO robot built in 2001 during the month of January. 60 other 2/3 person teams also built robots to compete in the double-elimination tournament. "Don't Worry" went through the entire competition undefeated and won first place. Through robust electro-mechanical design and optimized software code, we were able to realize our simple-yet-elegant strategy (heavily reliant on speed and hybrid closed-/open-loop controls). We also implemented a ``track-and-attack'' algorithm that engages after we score our points. The video to the left contains some highlights. |